View ADP5033_1956204.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dual 3 mhz, 800 ma buck regulators with two 300 ma ldos ADP5033 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features main input voltage range: 2.3 v to 5.5 v two 800 ma buck regulators and two 300 ma ldos tiny, 16-ball, 2 mm 2 mm wlcsp package regulator accuracy: 3% factory programmable voutx 3 mhz buck operation with forced pwm and auto pwm/psm modes buck1/buck2: output voltage range from 0.8 v to 3.3 v ldo1/ldo2: output voltage range from 0.8 v to 3.3v ldo1/ldo2: low input supply voltage from 1.7 v to 5.5 v ldo1/ldo2: high psrr and low output noise applications power for processors, asics, fpgas, and rf chipsets portable instrumentation and medical devices space constrained devices general description the ADP5033 combines two high performance buck regulators and two low dropout regulators (ldo) in a tiny, 16-ball, 2 mm 2 mm wlcsp to meet demanding performance and board space requirements. the high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space. when the mode pin is set high, the buck regulators operate in forced pwm mode. when the mode pin is set low, the buck regulators operate in qpxfstbwfnpef p 4 m
. when uifmpbejt around the nominal value and the load current falls cfmpxb predefined threshold, the regulator operates in 14. improving the light load efficiency. the tw o bucks operate out of phase to reduce the input capacitor requirement and noise. the low quiescent current, low dropout voltage, and wide input voltage range of the ADP5033 ldo extend the battery life of portable devices. the ADP5033 ldos maintain power supply rejection greater than 60 db for frequencies as high as 10 khz while operating with a low headroom voltage. the regulators in the ADP5033 are activated by the ena and enb pins. the specific channels controlled by ena and enb are set by factory programming. a high voltage level applied to the enable pins activates the regulators. the default output voltages are factory programmable and can be set to a wide range of options. typical application circuit vin1 2 .3v to 5.5 v sw1 vout1 pgnd1 mode c5 10f l1 1h buck1 c2 4.7f c1 4.7f vin2 agnd buck2 sw2 vout2 pgnd2 c6 10f l2 1h vout3 c7 1f vout4 c8 1f vin3 c3 1f 1.7v to 5.5v ldo1 (analog) vin4 c4 1f a dp5033 ena activ. and uvlo enb on off psm/pwm pwm en1 en2 en3 en4 ldo2 (digital) en2 en3 en4 mode mode vout1 @ 800ma vout2 @ 800ma vout3 @ 300ma vout4 @ 300ma 09788-001 figure 1. www..net
ADP5033 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? typical application circuit ............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? general specifications ................................................................. 3 ? buck1 and buck2 specifications ........................................... 4 ? ldo1 and ldo2 specifications................................................. 4 ? input and output capacitor, recommended specifications.. 5 ? absolute maximum ratings............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution.................................................................................. 6 ? pin configuration and function descriptions............................. 7 ? typical performance characteristics ............................................. 8 ? power dissipation and thermal considerations ....................... 15 ? buck regulator power dissipation .......................................... 15 ? junction temperature ................................................................ 16 ? theory of operation ...................................................................... 17 ? power management unit........................................................... 17 ? buck1 and buck2 .................................................................. 18 ? ldo1 and ldo2........................................................................ 19 ? applications information .............................................................. 20 ? buck external component selection....................................... 20 ? ldo capacitor selection .......................................................... 22 ? pcb layout guidelines.................................................................. 23 ? typical application schematic ..................................................... 24 ? outline dimensions ....................................................................... 25 ? ordering guide .......................................................................... 25 ? revision history 5/11revision 0: initial version
ADP5033 rev. 0 | page 3 of 28 specifications general specifications v in1 = v in2 = v in3 = v in4 = 2.3 v to 5.5 v; v in3 = v in4 = 1.7 v to 5.5 v; t j = ?40c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit input voltage range v in1 , v in2 2.3 5.5 v thermal shutdown threshold ts sd t j rising 150 c hysteresis ts sd-hys 20 c start-up time 1 buck1, ldo1, ldo2 t start1 250 s buck2 t start2 300 s ena, enb, mode inputs input logic high v ih 1.1 v input logic low v il 0.4 v input leakage current v i-leakage 0.05 1 a standby current all channels enabled i stby-nosw no load, no buck switching 108 175 a all channels disabled i shutdown t j = ?40c to +85c 0.3 1 a vin1 undervoltage lockout high uvlo input voltage rising uvlo vin1rise 3.9 v high uvlo input voltage falling uvlo vin1fall 3.1 v low uvlo input voltage rising uvlo vin1rise 2.275 v low uvlo input voltage falling uvlo vin1fall 1.95 v 1 start-up time is defined as the time from v in1 > uvlo vin1rise to vout1, vout2, vout3, and vout4 reaching 90% of their nominal levels.
ADP5033 rev. 0 | page 4 of 28 buck1 and buck2 specifications v in1 = v in2 = 2.3 v to 5.5 v; t j = ?40c to +125c for minimum/maximum specications, and t a = 25c for typical specifications, unless otherwise noted. 1 table 2. parameter symbol test conditions/comments min typ max unit input characteristics input voltage range v in1 , v in2 pwm mode, i load1 = i load2 = 0 ma to 800 ma 2.3 5.5 v output characteristics output voltage accuracy v out1 , v out2 pwm mode; v in1 = v in2 = 2.3 v to 5.5 v; i load1 = i load2 = 0 ma to 800 ma ?3 +3 % line regulation v out1 , v out2 pwm mode ?0.05 %/v load regulation i out1 , i out2 i load = 0 ma to 800ma, pwm mode ?0.1 %/a psm current threshold psm to pwm operation i psm 100 ma operating supply current mode = ground buck1 only i in i load1 = 0 ma, device not switching, all other channels disabled. 44 a buck2 only i in i load2 = 0 ma, device not switching, all other channels disabled. 55 a buck1 and buck2 i in i load1 = i load2 = 0 ma, device not switching, ld o channels disabled. 67 a sw characteristics sw on resistance r pfet pfet at vin1 = 5 v 145 235 m r pfet pfet at vin1 = 3.6 v 180 295 m r nfet nfet at vin1 = 5 v 110 190 m r nfet nfet at vin1 = 3.6 v 125 220 m current limit i limit1 , i limit2 pfet switch peak current limit 1100 1350 ma active pull-down r pdwn-b channel disabled 75 oscillator frequency f sw 2.5 3.0 3.5 mhz 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). ldo1 and ldo2 specifications v in3 = (v out3 + 0.5 v) or 1.7 v (whichever is greater) to 5.5 v, v in4 = (v out4 + 0.5 v) or 1.7 v (whichever is greater) to 5.5 v; c in = c out = 1 f; t j = ?40c to +125c for minimum/maximum specications, and t a = 25c for typical specifications, unless otherwise noted. 1 table 3. parameter symbol test conditions/comments min typ max unit input voltage range v in3 , v in4 1.7 5.5 v operating supply current bias current per ldo 2 i vin3bias /i vin4bias i out3 = i out4 = 0 a 10 30 a i out3 = i out4 = 10 ma 60 100 a i out3 = i out4 = 300 ma 165 245 a total system input current i in includes all current into vin1, vin2, vin3, and vin4 ldo1 or ldo2 only i out3 = i out4 = 0 a, all other channels disabled 53 a ldo1 and ldo2 only i out3 = i out4 = 0 a, buck channels disabled 74 a output characteristics output voltage accuracy v out3 , v out4 100 a < i out3 < 300 ma, 100 a < i out4 < 300 ma; v in3 = (v out3 + 0.5 v) to 5.5 v, v in4 = (v out4 + 0.5 v) to 5.5 v ?3 +3 % line regulation ?v out3 /?v in3 , ?v out4 /?v in4 v in3 = (v out3 + 0.5 v) to 5.5 v, v in4 = (v out4 + 0.5 v) to 5.5 v, i out3 = i out4 = 1 ma ?0.03 +0.03 %/ v load regulation 3 ?v out3 /?i out3 , ?v out4 /?i out4 i out3 = i out4 = 1 ma to 300 ma 0.001 0.003 %/ma dropout voltage 4 v dropout v out3 = v out4 = 3.3 v 65 110 mv v out3 = v out4 = 2.5 v 85 mv v out3 = v out4 = 1.8 v 165 mv current-limit threshold 5 i limit3 , i limit4 335 600 ma active pull-down r pdwn-l channel disabled 600
ADP5033 rev. 0 | page 5 of 28 parameter symbol test conditions/comments min typ max unit power supply rejection ratio psrr regulator ldo1 10 khz, v in3 = 3.3 v, v out3 = 2.8 v, i out3 = 1 ma 60 db 100 khz, v in3 = 3.3 v, v out3 = 2.8 v, i out3 = 1 ma 62 db 1 mhz, v in3 = 3.3 v, v out3 = 2.8 v, i out3 = 1 ma 63 db regulator ldo2 10 khz, v in4 = 1.8 v, v out4 = 1.2 v, i out4 = 1 ma 54 db 100 khz, v in4 = 1.8 v, v out4 = 1.2 v, i out4 = 1 ma 57 db 1 mhz, v in4 = 1.8 v, v out4 = 1.2 v, i out4 = 1 ma 64 db 1 all limits at temperature extremes ar e guaranteed via correlatio n using standard statistical quality control (sqc). 2 2 this is the input current into vin3/vin4, which is not delivered to the output load. 3 based on an en dpoint calculation using 1 ma and 100 ma loads. 4 dropout voltage is defined as the input-to-output voltage differe ntial when the input voltage is set to the nominal output vol tage. this applies only to output voltages above 1.7 v. 5 current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 3.0 v output voltage is defined as the curre nt that causes the output voltage to drop to 90% of 3.0 v, or 2.7 v. input and output capacitor, recommended specifications t a = ?40c to +125c, unless otherwise specified. table 4. parameter symbol min typ max unit suggested input and output capacitance buck1, buck2 input capacitor c min1 , c min2 4.7 40 f buck1, buck2 output capacitor c min1 , c min2 10 40 f ldo1, ldo2 1 input and output capacitors c min3 , c min4 0.70 f capacitor esr r esr 0.001 1 1 the minimum input and output capacitance should be greater than 0.70 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during devi ce selection to ensure that the minimum capa citance specification is met. x7r- and x5 r-type capacitors are recommended; y5v and z5u capacitors are not recommended for use with ldos.
ADP5033 rev. 0 | page 6 of 28 absolute maximum ratings table 5. parameter rating vin1, vin2, vin3, vin4, vout1, vout2, vout3, vout4, ena, mode, enb to ground C0.3 v to +6 v storage temperature range C65c to +150c operating junction temperature range C40c to +125c soldering conditions jedec j-std-020 esd human body model 1500 v esd charged device model 500 v esd machine model 100 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for detailed information on power dissipation, see the power dissipation and thermal considerations section. thermal resistance ja and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 6. thermal resistance package type ja jb unit 16-ball, 0.5 mm pitch wlcsp 57 14 c/w esd caution
ADP5033 rev. 0 | page 7 of 28 pin configuration and fu nction descriptions top view (ball side down) not to scale 1 a b c d 234 ball a1 indicator vout3 agnd vin1 pgnd1 vin4 ena vout2 sw2 vout4 enb vin2 pgnd2 vin3 mode vout1 sw1 09788-002 figure 2. pin configurationview from the top of the die table 7. pin function descriptions pin no. mnemonic description a1 vout3 ldo1 output vo ltage and sensing input. a2 vin3 ldo1 input supply (1.7 v to 5.5 v, vin4 vin1 = vin2). a3 vin4 ldo2 input supply (1.7 v to 5.5 v, vin3 vin1 = vin2). a3 vout4 ldo2 output vo ltage and sensing input. b1 agnd analog ground. b2 mode buck1/buck2 operating mode. mode = high: forced pwm operation. mode = low: auto pwm/psm operation. b3 ena regulator enable pin a, active high. the regulators turned on with ena are factory programmed. b4 enb regulator enable pin b, active high. the regulators turned on with enb are factory programmed. c1 vin1 buck1 input supply (2.3 v to 5.5 v) and uvlo detection. connect vin1 to vin2. c2 vout1 buck1 output voltage sensing input. c3 vout2 buck2 output voltage sensing input. c4 vin2 buck2 input supply (2.3 v to 5.5 v). connect vin2 to vin1. d1 pgnd1 dedicated power ground for buck1. d2 sw1 buck1 switching node. d3 sw2 buck2 switching node. d4 pgnd2 dedicated power ground for buck2.
ADP5033 rev. 0 | page 8 of 28 typical performance characteristics v in1 = v in2 = v in3 = v in4 = 5.0 v, t a = 25c, unless otherwise noted. 09788-139 0 20 40 60 80 100 120 140 2.3 2.8 3.3 3.8 4.3 4.8 5.3 input voltage (v) quiescent current (a) figure 3. system quiescent current vs. input voltage, v out1 = 3.3 v, v out2 = 1.8 v, v out3 = 1.2 v, v out4 = 3.3 v, all channels unloaded 4 1 3 t 2 ch1 2.00v ch4 5.00v m 40.0s a ch3 2.2v t 11.20% ch2 50.0ma ? ch3 5.00v sw vout en i in 09788-021 figure 4. buck1 startup, v out1 = 3.3 v, i out1 = 10 ma 4 1 3 t 2 ch1 2.00v ch4 5.00v m 40.0s a ch3 2.2v t 11.20% ch2 50.0ma ? ch3 5.00v sw vout en i in 09788-020 figure 5. buck2 startup, v out2 = 1.8 v, i out2 = 5 ma 3.35 3.33 3.31 3.29 3.27 3.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i out (a) v out a (v) v in = 4.2v, +25c v in = 4.2v, +85c v in = 4.2v, ?40c 09788-058 figure 6. buck1 load regulation across temperature, v out1 = 3.3 v, auto mode 1.864 1.764 1.784 1.804 1.824 1.844 0 0.10.20.30.40.50.60.7 0.8 i out (a) v out a (v) v in = 3.6v, +25c v in = 3.6v, +85c v in = 3.6v, ?40c 09788-057 figure 7. buck2 load regulation across temperature, v out2 = 1.8 v, auto mode 0.799 0.789 0.791 0.793 0.795 0.797 0.798 0.790 0.792 0.794 0.796 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 i out (a) v out a (v) v in = 3.6v, +25c v in = 3.6v, +85c v in = 3.6v, ?40c 09788-054 figure 8. buck1 load regulation across input voltage, v out1 = 3.3 v, pwm mode
ADP5033 rev. 0 | page 9 of 28 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 i out (a) efficiency (%) v in = 3.9v v in = 4.2v v in = 5.5v 09788-038 figure 9. buck1 efficiency vs. load current, across input voltage, v out1 = 3.3 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) v in = 3.9v v in = 4.2v v in = 5.5v 09788-039 figure 10. buck1 efficiency vs. lo ad current, across input voltage, v out1 = 3.3 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v 09788-036 figure 11. buck2 efficiency vs. lo ad current, across input voltage, v out2 = 1.8 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v 09788-035 figure 12. buck2 efficiency vs. lo ad current, across input voltage, v out2 = 1.8 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v 09788-034 figure 13. buck1 efficiency vs. lo ad current, across input voltage, v out1 = 0.8 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) v in = 2.3v v in = 3.6v v in = 4.2v v in = 5.5v 09788-065 figure 14. buck1 efficiency vs. lo ad current, across input voltage, v out1 = 0.8 v, pwm mode
ADP5033 rev. 0 | page 10 of 28 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) +25c +85c ?40c 09788-062 figure 15. buck1 efficiency vs. load current, across temperature, v out1 = 3.3 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) +25c +85c ?40c 09788-063 figure 16. buck2 efficiency vs. load current, across temperature, v out2 = 1.8 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) +25c +85c ?40c 09788-200 figure 17. buck2 efficiency vs. load current, across temperature, 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 01 1.0 0.8 0.6 0.4 0.2 i out (a) frequency (mhz) . 2 t a = +25c t a = ?40c t a = +85c 09788-040 figure 18. buck2 switching frequency vs. output current, across temperature, v out2 = 1.8 v, pwm mode 2 4 t 1 ch1 50.0v m 4.00s a ch2 240ma t 28.40% ch2 500ma ? ch4 2.00v i sw vout sw 09788-025 figure 19. typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, auto mode 2 4 t 1 ch1 50.0v m 4.00s a ch2 220ma t 28.40% ch2 500ma ? ch4 2.00v i sw vout sw 09788-024 figure 20. typical waveforms, v out2 = 1.8 v, i out2 = 30 ma, auto mode
ADP5033 rev. 0 | page 11 of 28 2 4 t 1 ch1 50mv m 400ns a ch2 220ma t 28.40% ch2 500ma ? ch4 2.00v i sw vout sw 09788-027 figure 21. typical waveforms, v out1 = 3.3 v, i out1 = 30 ma, pwm mode 2 4 t 1 ch1 50mv m 400ns a ch2 220ma t 28.40% ch2 500ma ? ch4 2.00v i sw vout sw 09788-026 figure 22. typical waveforms, vout2 = 1.8 v, i out2 = 30 ma, pwm mode ch1 50.0mv ch3 1.00v ch4 2.00v m 1.00ms a ch3 4.80v 1 3 t 30.40% t vout vin sw 09788-012 figure 23. buck1 response to line tr ansient, input voltage from 4.5 v to 5.0 v, v out1 = 3.3 v, pwm mode 1 4 t 3 ch1 50.0mv ch3 1.00v ch4 2.00v m 1.00ms a ch3 4.80v t 30.40% vout vin sw 09788-013 figure 24. buck2 response to line transient, v in = 4.5 v to 5.0 v, v out2 = 1.8 v, pwm mode 4 1 t 2 ch1 50.0mv ch4 5.00v m 20.0s a ch2 356ma t 60.000s ch2 50.0ma ? vout i out sw 09788-016 figure 25. buck1 response to load transient, i out1 from 1 ma to 50 ma, v out1 = 3.3 v, auto mode 4 1 t 2 ch1 50.0mv ch4 5.00v m 20.0s a ch2 379ma t 22.20% ch2 50.0ma ? vout i out sw 0 9788-015 figure 26. buck2 response to load transient, i out2 from 1 ma to 50 ma, v out2 = 1.8 v, auto mode
ADP5033 rev. 0 | page 12 of 28 4 2 t 1 ch1 50.0mv ch4 5.00v m 20.0s a ch2 408ma t 20.40% ch2 200ma ? vout i out sw 0 9788-017 figure 27. buck1 response to load transient, i out1 from 20 ma to 180 ma, v out1 = 3.3 v, auto mode 4 2 t 1 ch1 100mv ch4 5.00v m 20.0s a ch2 88.0ma t 19.20% ch2 200ma ? vout i out sw 09788-018 figure 28. buck2 response to load transient, i out2 from 20 ma to 180 ma, v out2 = 1.8 v, auto mode 4 1 3 t 2 ch1 5.00v ch4 5.00v m 400ns a ch4 1.90v t 50.00% ch2 5.00v ch3 5.00v vout1 vout2 sw1 sw2 09788-066 figure 29. vout and sw waveforms for buck1 and buck2 in pwm mode showing out-of-phase operation 2 3 t 1 ch1 2.00v m 40.0s a ch3 2.2v t 11.20% ch2 50.0ma ? ch3 5.00v vout en i in 09788-022 figure 30. ldo startup, vout3 = 3.0 v, i out3 = 5 ma 2.820 2.780 2.785 2.790 2.795 2.800 2.805 2.810 2.815 0 0.05 0.10 0.15 0.20 0.25 0.30 i out (a) v out c (v) v in = 3.3v v in = 4.5v v in = 5.0v v in = 5.5v 09788-046 figure 31. ldo load regulation across input voltage, v out3 = 2.8 v 3.45 3.15 3.20 3.25 3.30 3.35 3.40 00 0.25 0.20 0.15 0.10 0.05 i out (a) v out d (v) . 3 0 v in = 4.2v, +25c v in = 4.2v, +85c v in = 4.2v, ?40c 09788-049 figure 32. ldo load regulation across temperature, v in3 = 3.3 v, v out3 = 2.8 v
ADP5033 rev. 0 | page 13 of 28 3.0 2.5 2.0 1.5 1.0 0.5 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 v in (v) v out c (v) i out = 300ma i out = 150ma i out = 100ma i out = 10ma i out = 1ma i out = 100a 09788-045 figure 33. ldo line regula tion across output load, v out3 = 2.8 v 0 0.05 0.10 0.15 0.20 0.25 ground current (a) load current (a) 09788-136 0 5 10 15 20 25 30 35 40 45 50 figure 34. ldo ground current vs. output load, v in3 = 3.3 v, v out3 = 2.8 v 2 t 1 ch1 100mv m 40.0s a ch2 52.0ma t 19.20% ch2 100ma ? vout i out 09788-019 figure 35. ldo response to load transient, i out3 from 1 ma to 80 ma, v out3 = 2.8 v 2 3 t 1 ch1 20.0mv ch3 1.00v m 100s a ch3 4.80v t 28.40% vout vin 09788-014 figure 36. ldo response to line transient, input voltage from 4.5 v to 5.5 v, v out3 = 2.8 v 60 55 50 45 40 35 30 25 0.001 0.01 0.1 1 10 100 i load (ma) rms noise (v) 3.3vin 5vin 09788-047 figure 37. ldo output noise vs. load current, across input voltage, v out3 = 2.8 v 60 65 55 50 45 40 35 30 25 0.001 0.01 0.1 1 10 100 i load (ma) rms noise (v) 5vin 3.3vin 09788-048 figure 38. ldo output noise vs. load current, across input voltage, v out3 = 3.0 v
ADP5033 rev. 0 | page 14 of 28 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 100a 1ma 10ma 50ma 100ma 150ma 09788-050 figure 39. ldo psrr across output load, v in3 = 3.3 v, v out3 = 2.8 v 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 100a 1ma 10ma 50ma 100ma 150ma 09788-051 figure 40. ldo psrr across output load, v in3 = 3.3 v, v out3 = 3.0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 100a 1ma 10ma 50ma 100ma 150ma 09788-053 figure 41. ldo psrr across output load, v in3 = 5.0 v, v out3 = 2.8 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 100a 1ma 10ma 50ma 100ma 150ma 09788-052 figure 42. ldo psrr across output load, v in3 = 5.0 v, v out3 = 3.0 v
ADP5033 rev. 0 | page 15 of 28 power dissipation and thermal considerations the ADP5033 is a highly efficient micropower management unit (pmu), and, in most cases, the power dissipated in the device is not a concern. however, if the device operates at high ambient temperatures and maximum loading condition, the junction temperature can reach the maximum allowable operating limit (125c). when the temperature exceeds 150c, the ADP5033 turns off all the regulators, allowing the device to cool down. when the die temperature falls below 130c, the ADP5033 resumes normal operation. this section provides guidelines to calculate the power dissi- pated in the device and ensure that the ADP5033 operates below the maximum allowable junction temperature. the efficiency for each regulator on the ADP5033 is given by 100% = in out p p (1) ) is the rms load curren where: is the efficiency. p in is the input power. p out is the output power. power loss is given by p loss = p in ? p out (2a) or p loss = p out (1? )/ (2b) power dissipation can be calculated in several ways. the most intuitive and practical is to measure the power dissipated at the input and all the outputs. perform the measurements at the worst-case conditions (voltages, currents, and temperature). the difference between input and output power is dissipated in the device and the inductor. use equation 4 to derive the power lost in the inductor and, from this, use equation 3 to calculate the power dissipation in the ADP5033 buck converter. a second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, and the power lost on each ldo can be calculated using equation 12. when the buck efficiency is known, use equation 2b to derive the total power lost in the buck regulator and inductor, use equation 4 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using equation 3. add the power dissipated in the buck and in the two ldos to find the total dissipated power. note that the buck efficiency curves are typical values and may not be provided for all possible combinations of v in , v out , and i out. to account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. a third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by buck regulator power dissipation the power loss of equation 8 to equation 11 and the losses in the ldo provided by equation 12. the buck regulator is approximated by (3) p dbu rs. r losses are external to the device, and they do not ature. (4) dcr t of the buck regulator. p loss = p dbuck1 + p dbuck2 + p l where: ck is the power dissipation on one of the ADP5033 buck regulato p l is the inductor power losses. the inducto have any effect on the die temper the inductor losses are estimated (without core losses) by p l i out1(rms) 2 dcr l where: l is the inductor series resistance. i out1(rms 12 +1 )(1 r i i out1 rmsout = (5) where r is the inductor ripple cur t r v out1 (1 ? d )/( i out1 l f sw ) (6) witching frequency. (7) lator power dissipation, p dbuck , includes the pow (8) to the output current, i out (9) i- mate ren where: l is t he inductance. f sw is the s d is the duty cycle. d = v out1 / v in1 ADP5033 buck regu er switch conductive losses, the switch losses, and the transi- tion losses of each channel. there are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator. p dbuck = p cond + p sw + p tran the power switch conductive losses are due 1 , flowing through the p-mosfet and the n-mosfet power switches that have internal resistance, rds on-p and rds on-n . the amount of conductive power loss is found by p cond = [ rds on-p d + rds on-n (1 ? d )] i out1 2 where rds on-p is approximately 0.2 , and rds on-n is approx ly 0.16 at 125c junction temperature and vin1 = vin2 = 3.6 v. at vin1 = vin2 = 2.3 v, these values change to 0.31 and 0.21 , respectively, and at vin1 = vin2 = 5.5 v, the values are 0.16 and 0.14 , respectively.
ADP5033 rev. 0 | page 16 of 28 witching losses are associated with the current drawn by the (10) whe the p-mosfet gate capacitance. e-n ) is approxi- osses occur because the p-channel power he t1 ( t rise + t fall ) f sw (11) whe fall time of the s of d parameters are used for estimat- dissipation ven by ) (12) whe he load current of the ldo regulator. e ldo, all, and it s driver to turn on and turn off the power devices at the switching frequency. the amount of switching power loss is given by p sw = ( c gate-p + c gate-n ) v in1 2 f sw re: c gate-p is c gate-n is the n-mosfet gate capacitance. for the ADP5033, the total of ( c gate-p + c gat mately 150 pf. the transition l mosfet cannot be turned on or off instantaneously, and t sw node takes some time to slew from near ground to near v out1 (and from v out1 to ground). the amount of transition loss is calculated by p tran = v in1 i ou re t rise and t fall are the rise time and the switching node, sw. for the ADP5033, the rise and fall time sw are in the order of 5 ns. if the preceding equations an ing the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. the converter performance also depends on the choice of passive components and board layout; therefore, a sufficient safety margin should be included in the estimate. ldo regulator power the power loss of a ldo regulator is gi p dldo = [( v in ? v out ) i load ] + ( v in i gnd re: i load is t v in and v out are input and output voltages of th respectively. i gnd is the ground current of the ldo regulator. power dissipation due to the ground current is sm can be ignored. junction temperature the total power dissipation in the ADP5033 simplifies to p d = p dbuck + p dldo1 + p dldo2 (13) in cases where the board temperature t a is known, the thermal resistance parameter, ja , can be used to estimate the junction temperature rise. t j is calculated from t a and p d using the formula t j = t a + ( p d ja ) (14) the typical ja value for the 16-ball, 0.5 mm pitch wlcsp is 57c/w (see table 6 ). a very important factor to consider is that ja is based on a 4-layer 4 in 3 in, 2.5 oz copper, as per jedec standard, and real applications may use different sizes and layers. it is important to maximize the copper used to remove the heat from the device. copper exposed to air dissipates heat better than copper used in the inner layers. the exposed pad should be connected to the ground plane with several vias. if the case temperature can be measured, the junction tempera- ture is calculated by t j = t c + ( p d jb ) (15) where t c is the case temperature and jb is the junction-to- board thermal resistance provided in table 6 . when designing an application for a particular ambient temperature range, calculate the expected ADP5033 power dissipation (p d ) due to the losses of all channels by using the equation 8 to equation 13. from this power calculation, the junction temperature, t j , can be estimated using equation 14. the reliable operation of the converter and the two ldo regulators can be achieved only if the estimated die junction temperature of the ADP5033 (equation 14) is less than 125c. reliability and mean time between failures (mtbf) is highly affected by increas- ing the junction temperature. additional information about product reliability can be found in the adi reliability handbook , which can be found at www.analog.com/reliability_handbook .
ADP5033 rev. 0 | page 17 of 28 theory of operation enable and mode control ldo control ldo undervoltage lock out soft start pwm/ psm control buck2 driver and antishoot through soft start pwm/ psm control buck1 driver and antishoot through oscillator thermal shutdown system undervoltage lockout pwm comp gm error amp gm error amp psm comp psm comp low current i limit pwm comp low current i limit r1 r2 ADP5033 v out1 v out2 vin1 sw1 pgnd1 ena enbk1 enbk2 enldo1 enldo2 enb vdda vin3 agnd vout3 pgnd2 mode sw2 vin2 ldo control ldo undervoltage lock out r3 r4 vdda vin4 vout4 enldo1 600 ? enbk2 75 ? enbk1 75 ? enldo1 600 ? b a y sel opmode mode2 09788-003 vdda figure 43. functional block diagram power management unit the ADP5033 is a micropower management unit (pmu) combing two step-down (buck) dc-to-dc convertors and two low dropout linear regulators (ldo). the high switching frequency and tiny 16-ball wlcsp package allow for a small power management solution. to combine these high performance regulators into the pmu, there is a system controller allowing them to operate together. the buck regulators can operate in forced pwm mode if the mode pin is at a logic high level. in forced pwm mode, the buck switching frequency is always constant and does not change with the load current. if the mode pin is at logic low, the switching regulators operate in auto pwm/psm mode. in this mode, the regulators operate at fixed pwm frequency when the load current is above the power saving current thresh- old. when the load current falls below the power save current threshold, the regulator in question enters psm where the switching occurs in bursts. the burst repetition is a function of the current load and the output capacitor value. this operating mode reduces the switching and quiescent cur- rent losses. the auto pwm/psm mode transition is controlled independently for each buck regulator. the two bucks operate synchronized to each other. when a regulator is turned on, the output voltage ramp is controlled through a soft start circuit to avoid a large inrush current due to the charging of the output capacitors. thermal protection in the event that the junction temperature rises above 150c, the thermal shutdown circuit turns off all the regulators. extreme junction temperatures can be the result of high current opera- tion, poor circuit board design, or high ambient temperature. a 20c hysteresis is included so that when thermal shutdown occurs, the regulators do not return to operation until the on-chip temperature drops below 130c. when coming out of thermal shutdown, all regulators restart with soft start control.
ADP5033 rev. 0 | page 18 of 28 undervoltage lockout to protect against battery discharge, undervoltage lockout (uvlo) circuitry is integrated in the system. if the input voltage on vin1 drops below a typical 2.15 v uvlo threshold, all channels shut down. in the buck channels, both the power switch and the synchronous rectifier turn off. when the voltage on vin1 rises above the uvlo threshold, the part is enabled once more. alternatively, the user can select device models with a uvlo set at a higher level, suitable for usb applications. for these models, the device reaches the turn-off threshold when the input supply drops to 3.65 v typical. in case of a thermal or uvlo event, the active pull-downs (if factory enabled) are enabled to discharge the output capacitors quickly. the pull-downs remain engaged until the input supply voltage or thermal fault event is no longer present. enable/shutdown the ADP5033 has two enable pins (ena and enb). a high level applied to the enable pins enables a certain selection of regulators defined by factory programming. for example, the ADP5033 can be factory programmed to enable buck1 and ldo2 with ena and buck2 and ldo1 with enb. when both enables are low, all regulators are turned off. when both enable pins are high, all regulators are turned on. all possible regulator combinations can be factory programmed to operate with the ena and enb pins. figure 44 shows the regulator activation timings for the ADP5033 when both enables are connected to vinx. figure 44 also shows the active pull-down activation. buck1 and buck2 the two bucks use a fixed frequency and high speed current mode architecture. the bucks operate with an input voltage of 2.3 v to 5.5 v. control scheme the bucks operate with a fixed frequency, current mode pwm control architecture at medium to high loads for high efficiency but shift to a psm control scheme at light loads to lower the regulation power losses. when operating in fixed frequency pwm mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. when operating in psm at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. during part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. pwm mode in pwm mode, the bucks operate at a fixed frequency of 3 mhz set by an internal oscillator. at the start of each oscillator cycle, the pfet switch is turned on, sending a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pfet switch and turns on the nfet synchronous rectifier. this sends a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle. the buck regulates the output voltage by adjusting the peak inductor current threshold. vin1 vout3 vout4 vout1 vuvlo vout2 vpor buck2 pull-down buck1, ldo1, ldo2 pull-downs 50s (min) 30s (min) 50s (min) 30s (min) 09788-148 figure 44. regulators sequencing on the ADP5033 (enx = vinx)
ADP5033 rev. 0 | page 19 of 28 psm the bucks smoothly transition to psm operation when the load current decreases below the psm current threshold. when either of the bucks enters psm, an offset is induced in the pwm regulation level, which makes the output voltage rise. when the output voltage reaches a level approximately 1.5% above the pwm regulation level, pwm operation is turned off. at this point, both power switches are off, and the buck enters an idle mode. the output capacitor discharges until the output voltage falls to the pwm regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. this process is repeated while the load current is below the psm current threshold. the ADP5033 has a dedicated mode pin controlling the psm and pwm operation. a high logic level applied to the mode pin forces both bucks to operate in pwm mode. a logic level low sets the bucks to operate in auto psm/pwm. psm current threshold the psm current threshold is set to100 ma. the bucks employ a scheme that enables this current to remain accurately con- trolled, independent of input and output voltage levels. this scheme also ensures that there is very little hysteresis between the psm current threshold for entry to and exit from the psm. the psm current threshold is optimized for excellent efficiency over all load currents. oscillator/phasing of inductor switching the ADP5033 ensures that both bucks operate at the same switching frequency when both bucks are in pwm mode. additionally, the ADP5033 ensures that when both bucks are in pwm mode, they operate out of phase, whereby the buck2 pfet starts conducting exactly half a clock period after the buck1 pfet starts conducting. short-circuit protection the bucks include frequency foldback to prevent output current runaway on a hard short. when the voltage at the feedback pin falls below half the target output voltage, indicating the possi- bility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. the reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. soft start the bucks have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. current limit each buck has protection circuitry to limit the amount of positive current flowing through the pfet switch and the amount of negative current flowing through the synchronous rectifier. the positive current limit on the power switch limits the amount of current that can flow from the input to the output. the negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% duty operation with a dropin input voltage or with an increase in load current, the buck may reach a limit where, even with the pfet switch on 100% of the time, the output voltage drops below the desired output voltage. at this limit, the buck transitions to a mode where the pfet switch stays on 100% of the time. when the input conditions change again and the required duty cycle falls, the buck immediately restarts pwm regulation without allowing overshoot on the output voltage. active pull-downs all regulators have optional, factory programmable, active pull- down resistors discharging the respective output capacitors when the regulators are disabled by the enx pins or by a faulty condition. the pull-down resistors are connected between voutx and agnd. active pull-downs are disabled when the regulators are turned on. the typical value of the pull-down resistor is 600 for the ldos and 75 for the bucks. figure 44 shows the activation timings for the active pull-down during regulator activation and deactivation. ldo1 and ldo2 the ADP5033 contains two ldos with low quiescent current and two low dropout linear regulators and provides up to 300 ma of output current. drawing a low 25 a quiescent current (typical) at no load makes the ldo ideal for battery- operated portable equipment. each ldo operates with an input voltage of 1.7 v to 5.5 v. the wide operating range makes these ldos suitable for cascading configurations where the ldo supply voltage is provided from one of the buck regulators. each ldo also provides high power supply rejection ratio (psrr), low output noise, and excellent line and load transient response with just a small 1 f ceramic input and output capacitor. ldo1 is optimized to supply analog circuits because it offers better noise performance compared to ldo2. ldo1 should be used in applications where noise performance is critical.
ADP5033 rev. 0 | page 20 of 28 applications information buck external component selection trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in figure 1 . inductor the high switching frequency of the ADP5033 bucks allows for the selection of small chip inductors. for best performance, use inductor values between 0.7 h and 3 h. suggested inductors are shown in table 8 . the peak-to-peak inductor current ripple is calculated using the following equation: lfv vvv i sw in out in out ripple ? = ) ( where: f sw is the switching frequency. l is the inductor value. the minimum dc current rating of the inductor must be greater than the inductor peak current. the inductor peak current is calculated using the following equation: 2 )( ripple max load peak i ii + = inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (dcr). larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losses are related to the magnetic permeability of the core material. because the bucks are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low emi. table 8. suggested 1.0 h inductors vendor model dimensions (mm) i sat (ma) dcr (m) murata lqm2mpn1r0ng0b 2.0 1.6 0.9 1400 85 murata lqm18fn1r0m00b 1.6 0.8 0.8 150 26 taiyo yuden brc1608t1r0m 1.6 0.8 0.8 520 180 coilcraft? epl2014-102ml 2.0 2.0 1.4 900 59 tdk glfr1608t1r0m-lr 1.6 0.8 0.8 230 80 coilcraft 0603ls-102 1.8 1.69 1.1 400 81 toko mdt2520-cn 2.5 2.0 1.2 1350 85 output capacitor higher output capacitor values reduce the output voltage ripple and improve load transient response. when choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. ceramic capacitors are manufactured with a variety of dielec- trics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recom- mended for best performance. y5v and z5u dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu- lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol ) where: c eff is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c out is 9.24 f at 1.8 v, as shown in figure 45 . substituting these values in the equation yields c eff = 9.24 f (1 ? 0.15) (1 ? 0.1) = 7.074 f to guarantee the performance of the bucks, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0 2 4 6 8 10 12 0123456 dc bias voltage (v) capacitance (f) 09788-004 figure 45. typical capacitor performance
ADP5033 rev. 0 | page 21 of 28 the peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: () out sw in ripple clf v v = 2 2 out sw ripple cf i = 8 capacitors with lower equivalent series resistance (esr) are preferred to guarantee low output voltage ripple, as shown in the following equation: ripple ripple cout i v esr the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 f and a maximum of 40 f. the buck regulators require 10 f output capacitors to guaran- tee stability and response to rapid load variations and to transition into and out of the pwm/psm modes. in certain applications, where one or both buck regulators power a processor, the operating state is known because it is controlled by software. in this condition, the processor can drive the mode pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 f to 4.7 f because the regulator does not expect a large load variation when working in psm mode (see figure 47 ). table 9. suggested 10 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j106 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 tdk x5r c1608jb0j106k 0603 6.3 panasonic x5r ecj1vb0j106m 0603 6.3
ADP5033 rev. 0 | page 22 of 28 input capacitor higher value input capacitors help to reduce the input voltage ripple and improve transient response. maximum input capacitor current is calculated using the following equation: in out in out max load cin v vvv ii )( )( ? to minimize supply noise, place the input capacitor as close to the vinx pin of the buck as possible. as with the output capacitor, a low esr capacitor is recommended. the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 f and a maximum of 10 f. a list of suggested capacitors is shown in table 10 . table 10. suggested 4.7 f capacitors vendor tpe odel case sie voltage rating v murata x5r grm188r60j475me19d 0402 6.3 taiyo yuden x5r jmk107bj475 0402 6.3 panasonic x5r ecj-0eb0j475m 0402 6.3 ldo capacitor selection output capacitor the ADP5033 ldos are designed for operation with small, space-saving ceramic capacitors, but function with most commonly used capacitors as long as care is taken with the esr value. the esr of the output capacitor affects the stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 or less is recommended to ensure the stability of the ADP5033. transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the ADP5033 to large changes in load current. input bypass capacitor connecting a 1 f capacitor from vin3 and vin4 to ground reduces the circuit sensitivity to printed circuit board (pcb) layout, especially when long input traces or a high source impedance is encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match it. table 11. suggested 1.0 f capacitors vendor tpe odel case sie voltage rating v murata x5r grm155b30j105k 0402 6.3 tdk x5r c1005jb0j105kt 0402 6.3 panasonic x5r ecj0eb0j105k 0402 6.3 taiyo yuden x5r lmk105bj105mv-f 0402 10.0 input and output capacitor properties use any good quality ceramic capacitors with the ADP5033 as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bias characteristics. figure 46 depicts the capacitance vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera- ture range and is not a function of package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 0 123456 dc bias voltage (v) capacitance (f) 09788-006 figure 46. capacitance vs. voltage characteristic use the following equation to determine the worst-case capa- citance accounting for capacitor variation over temperature, component tolerance, and voltage: c eff = c bias (1 ? tempco ) (1 ? tol ) where: c bias is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 0.94 f at 1.8 v, as shown in figure 46 . substituting these values into the following equation, c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the performance of the ADP5033, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
ADP5033 rev. 0 | page 23 of 28 pcb layout guidelines poor layout can affect ADP5033 performance, causing electro- magnetic interference (emi) and electromagnetic compatibility (emc) problems, ground bounce, and voltage losses. poor layout can also affect regulation and stability. a good layout is implemented using the following guidelines: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies, and large tracks act as antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connecting to the component side ground to further reduce noise interfer- ence on sensitive circuit nodes. ? connect vin1 and vin2 together close to the ic using short tracks.
ADP5033 rev. 0 | page 24 of 28 typical application schematic vin1 ena vin: 2.3v to 5.5v sw1 vout1 vcore vcore vio vio gpio pgnd1 mode c5 4.7f l1 1h buck1 act c2 4.7f c1 4.7f vin2 enb agnd buck2 on off sw2 vout2 pgnd2 c6 4.7f l2 1h vout3 c7 1f vout4 c8 1f processor vana vdig analog subsystem vin3 c3 1f from vio (1.7v min) ldo1 vin4 c4 1f from vcore (1.7v min) a dp5033 always on bk1 bk2 ld1 ld2 ldo2 09788-152 figure 47. processor system power management with psm/pwm control
ADP5033 rev. 0 | page 25 of 28 outline dimensions 013009-b a b c d 0.660 0.602 0.544 2.12 2.08 sq 2.04 0.380 0.352 0.324 12 3 4 bottom view (ball side up) top view (ball side down) 0.280 0.250 0.220 0.330 0.310 0.290 ball 1 identifier seating plane 0.04 nom coplanarity 0.50 ref 0.022 ref 1.50 ref figure 48. 16-ball wafer level chip scale package [wlcsp] back-coating included (cb-16-7) dimensions shown in millimeters ordering guide model 1 temperature range output voltage (v) 2 options ena controlled channels 3 package description package option branding code ADP5033acbz-1-r7 ?40c to +125c vout1: 1.2 v vout2: 3.3 v vout3: 2.8 v vout4: 1.8 v uvlo: 2.25 v pull-downs on all channels buck2, ldo1 16-ball wafer level chip scale package [wlcsp] cb-16-7 lhx ADP5033-1-evalz evaluation board 1 z = rohs compliant part. 2 for additional options, contact a local sales or distribution representative . additional options available are buck1 and buck2: 3.3 v, 3.0 v, 2.8 v, 2.5 v, 2.3 v, 2.0 v, 1.82 v, 1.8 v, 1.6 v, 1.5 v, 1.3 v, 1.2 v, 1.1 v, 1.0 v, 0.9 v, 0.8 v. ldo1 and ldo2: 3.3 v, 3.0 v, 2.9 v, 2.8 v, 2.775 v, 2.5 v, 2.0 v, 1.875 v, 1.8 v, 1.75 v, 1.7 v, 1.65 v, 1.6 v, 1.55 v, 1.5 v, 1.2 v. uvlo: 2.25 v or 3.9 v. active pull-down: yes/no. 3 ena activated channels (enb controls the other channels).
ADP5033 rev. 0 | page 26 of 28 notes
ADP5033 rev. 0 | page 27 of 28 notes
ADP5033 rev. 0 | page 28 of 28 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09788-0-5/11(0)

▲Up To Search▲

Price & Availability of ADP5033

	To Download ADP5033 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .